Power Compiler：门控时钟单元的识别

发布时间：2026/7/31 19:05:19
Power Compiler：门控时钟单元的识别 相关阅读Power Compilerhttps://blog.csdn.net/weixin_45791458/category_13013065.html?spm1001.2014.3001.5482简介在Power Compiler中门控时钟单元可以使用compile_ultra -gate_clock命令自动插入之后可以使用report_clock_gating -gating_elements命令查看门控时钟单元也可以使用report_cell命令查看门控时钟单元的clock_gating_logic属性显示为cg。但有些情况下门控时钟单元可能无法被正确识别下面给出了几个例子。RTL形式的门控时钟module gated_clock ( input clk, input rst_n, input d, input en, output reg out ); reg en_reg ; always (posedge clk,negedge rst_n) begin if (~rst_n) begin en_reg 0; end else begin en_reg en; end end wire clk_g clk en_reg; always (posedge clk_g,negedge rst_n) begin if (~rst_n) begin out 0; end else begin out d; end end endmodulePower Compiler无法识别这种形式的RTL描述推导出门控时钟单元也就是说无论在综合时是否使用-gate_clock选项综合结果中的与门不会被认为是门控时钟单元如图1所示。图1 RTL形式门控时钟下面是report_clock_gating -gating_elements命令的结果可以发现Power Compiler并没有识别到门控时钟单元。dc_shell report_clock_gating -gating_elements **************************************** Report : clock_gating -gating_elements Design : gated_clock Version: W-2024.09-SP2 Date : Sun Jul 27 01:49:42 2025 **************************************** Information: No Clock Gating Cell Found. Clock Gating Summary ------------------------------------------------------------ | Number of Clock gating elements | 0 | | | | | Number of Gated registers | 0 (0.00%) | | | | | Number of Ungated registers | 2 (100.00%) | | | | | Total number of registers | 2 | ------------------------------------------------------------ Clock Gating Report by Origin ------------------------------------------------------------------- | | Actual (%) | | | Count | ------------------------------------------------------------------- | Number of tool-inserted clock gating elements | 0 (0.00%) | | | | | Number of pre-existing clock gating elements | 0 (0.00%) | | | | | Number of gated registers | 0 (0.00%) | | | | | Number of tool-inserted gated registers | 0 (0.00%) | | | | | Number of pre-existing gated registers | 0 (0.00%) | | | | | Number of ungated registers | 2 (100.00%) | | | | | Number of registers | 2 | -------------------------------------------------------------------显式例化的门控时钟单元module gated_clock ( input clk, input rst_n, input d, input en, output reg out ); reg en_reg ; always (posedge clk,negedge rst_n) begin if (~rst_n) begin en_reg 0; end else begin en_reg en; end end TLATNTSCAX2 latch ( .E(en_reg), .SE(1b0), .CK(clk), .ECK(clk_g) ); always (posedge clk_g,negedge rst_n) begin if (~rst_n) begin out 0; end else begin out d; end end endmodulePower Compiler无法识别显式例化的门控单元即使逻辑库中该单元有库单元属性clock_gating_integrated_cell也就是说综合结果中的锁存器不会被认为是门控时钟单元如图2所示。图2 显式例化的门控时钟单元下面是report_clock_gating -gating_elements命令的结果可以发现Power Compiler并没有识别到门控时钟单元。dc_shell report_clock_gating -gating_elements **************************************** Report : clock_gating -gating_elements Design : gated_clock Version: W-2024.09-SP2 Date : Sun Jul 27 14:35:39 2025 **************************************** Information: No Clock Gating Cell Found. Clock Gating Summary ------------------------------------------------------------ | Number of Clock gating elements | 0 | | | | | Number of Gated registers | 0 (0.00%) | | | | | Number of Ungated registers | 2 (100.00%) | | | | | Total number of registers | 2 | ------------------------------------------------------------ Clock Gating Report by Origin ------------------------------------------------------------------- | | Actual (%) | | | Count | ------------------------------------------------------------------- | Number of tool-inserted clock gating elements | 0 (0.00%) | | | | | Number of pre-existing clock gating elements | 0 (0.00%) | | | | | Number of gated registers | 0 (0.00%) | | | | | Number of tool-inserted gated registers | 0 (0.00%) | | | | | Number of pre-existing gated registers | 0 (0.00%) | | | | | Number of ungated registers | 2 (100.00%) | | | | | Number of registers | 2 | -------------------------------------------------------------------门控时钟综合后保存为ASCII格式的网表module gated_clock ( input clk, input rst_n, input d, input en, output reg out ); reg en_reg ; always (posedge clk,negedge rst_n) begin if (~rst_n) begin en_reg 0; end else begin en_reg en; end end always (posedge clk,negedge rst_n) begin if (~rst_n) begin out 0; end else if(en_reg) begin out d; end end endmodule上面是Power Compiler可以识别的RTL描述综合时使用-gate_clock选项即可自动插入门控时钟单元如图3所示。图3 门控时钟综合结果下面是report_clock_gating -gating_elements命令的结果可以发现Power Compiler识别到了门控时钟单元这是自然的因为该门控时钟单元就是由Power Compiler自动插入的。dc_shell report_clock_gating -gating_elements **************************************** Report : clock_gating -gating_elements Design : gated_clock Version: W-2024.09-SP2 Date : Sun Jul 27 14:56:38 2025 **************************************** -------------------------------------------------------------------------------- Clock Gating Cell Report -------------------------------------------------------------------------------- Clock Gating Bank : clk_gate_out_reg ------------------- STYLE latch, MIN 1, MAX unlimited, OBS_DEPTH 5 INPUTS : clk_gate_out_reg/CLK clk clk_gate_out_reg/EN en_reg OUTPUTS : clk_gate_out_reg/ENCLK net18 -------------------------------------------------------------------------------- Clock Gating Summary ------------------------------------------------------------ | Number of Clock gating elements | 1 | | | | | Number of Gated registers | 1 (50.00%) | | | | | Number of Ungated registers | 1 (50.00%) | | | | | Total number of registers | 2 | ------------------------------------------------------------ Clock Gating Report by Origin ------------------------------------------------------------------- | | Actual (%) | | | Count | ------------------------------------------------------------------- | Number of tool-inserted clock gating elements | 1 (100.00%) | | | | | Number of pre-existing clock gating elements | 0 (0.00%) | | | | | Number of gated registers | 1 (50.00%) | | | | | Number of tool-inserted gated registers | 1 (50.00%) | | | | | Number of pre-existing gated registers | 0 (0.00%) | | | | | Number of ungated registers | 1 (50.00%) | | | | | Number of registers | 2 | -------------------------------------------------------------------可以将综合结果保存为ASCII格式的网表如下所示。///////////////////////////////////////////////////////////// // Created by: Synopsys DC Ultra(TM) in wire load mode // Version : W-2024.09-SP2 // Date : Sun Jul 27 14:54:13 2025 ///////////////////////////////////////////////////////////// module SNPS_CLOCK_GATE_HIGH_gated_clock ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; TLATNCAX2 latch ( .E(EN), .CK(CLK), .ECK(ENCLK) ); endmodule module gated_clock ( clk, rst_n, d, en, out ); input clk, rst_n, d, en; output out; wire en_reg, net18; SNPS_CLOCK_GATE_HIGH_gated_clock clk_gate_out_reg ( .CLK(clk), .EN(en_reg), .ENCLK(net18) ); DFFRQXL out_reg ( .D(d), .CK(net18), .RN(rst_n), .Q(out) ); DFFRQXL en_reg_reg ( .D(en), .CK(clk), .RN(rst_n), .Q(en_reg) ); endmodule但是再次读取设计后门控时钟单元又无法识别了这是因为将网表保存为ASCII格式会导致属性丢失保存为ddc格式则不会所以其实这种情况就类似于显式例化的门控时钟单元下面是report_clock_gating -gating_elements命令的结果。dc_shell report_clock_gating -gating_elements **************************************** Report : clock_gating -gating_elements Design : gated_clock Version: W-2024.09-SP2 Date : Sun Jul 27 15:14:12 2025 **************************************** Information: No Clock Gating Cell Found. Clock Gating Summary ------------------------------------------------------------ | Number of Clock gating elements | 0 | | | | | Number of Gated registers | 0 (0.00%) | | | | | Number of Ungated registers | 2 (100.00%) | | | | | Total number of registers | 2 | ------------------------------------------------------------ Clock Gating Report by Origin ------------------------------------------------------------------- | | Actual (%) | | | Count | ------------------------------------------------------------------- | Number of tool-inserted clock gating elements | 0 (0.00%) | | | | | Number of pre-existing clock gating elements | 0 (0.00%) | | | | | Number of gated registers | 0 (0.00%) | | | | | Number of tool-inserted gated registers | 0 (0.00%) | | | | | Number of pre-existing gated registers | 0 (0.00%) | | | | | Number of ungated registers | 2 (100.00%) | | | | | Number of registers | 2 | -------------------------------------------------------------------解决方法使用set_clock_gating_style命令配合identify_clock_gating命令自动识别使用不加选项的identify_clock_gating命令可以自动识别设计中的门控时钟单元需要注意的是时钟单元能被识别的前提条件是它能被Power Compiler自动插入。使用命令前无需用create_clock命令创建时钟但需先使用set_clock_gating_style命令设置门控时钟风格否则即使基本属性设置正确例如clock_gating_logic属性也会出现错误的属性设置例如clock_gating_latch_style属性、pwr_cg_max_fanout属性等。显式识别如果门控时钟单元的风格不允许Power Compiler自动插入则它不能被自动识别此时需要使用-gating_elements选项显式指定这种情况下identify_clock_gating命令会在指定单元上设置pwr_cg_preservation_type属性如果指定单元本可被自动识别却被显式识别工具会将其属性设为preserve此时属性可移除若指定单元无法自动识别而被显式识别属性设为unmodifiable_read_only此时属性无法移除。显式识别要求该单元至少有两个输入引脚和一个输出引脚且其中一个输入为时钟引脚这要求使用命令前用create_clock命令创建时钟且会带来额外优化限制。在完成了指定单元的显式识别后命令还会执行全设计范围的自动识别以查找其余时钟门控单元若有。与自动识别类似显式识别也需先使用set_clock_gating_style命令设置门控时钟风格。使用power_cg_auto_identify变量将power_cg_auto_identify变量设置为true相当于identify_clock_gating命令的自动识别只不过此时自动识别不会要显式执行命令它会在执行涉及时钟门控电路的命令时执行例如report_clock_gating命令。使用write_script命令不建议write_script命令可以将设计中的属性不包括用户自定义属性保存在脚本中以供恢复如果该属性能用命令恢复例如dont_touch属性则会在脚本中添加对应的命令大多数情况例如set_dont_touch命令如果该属性不能用特定命令恢复少数情况例如power_cg_max_fanout属性则会在脚本中添加set_attribute命令。如果使用该方法则不支持网表变更且一些属性无法恢复。下面是一个write_script命令输出的脚本。current_design module4 set_attribute -type int [current_design] power_cg_max_fanout 2048 set_attribute -type boolean [get_cells clk_gate_out1_reg] clock_gating_logic true ...

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